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Author	SHA1	Message	Date
Gulshan Yadav	89fc542da4	feat(compute): add model registry and training APIs Adds comprehensive model management and training capabilities: synor-compute (Rust): - ModelRegistry with pre-registered popular models - LLMs: Llama 3/3.1, Mistral, Mixtral, Qwen, DeepSeek, Phi, CodeLlama - Embedding: BGE, E5 - Image: Stable Diffusion XL, FLUX.1 - Speech: Whisper - Multi-modal: LLaVA - ModelInfo with parameters, format, precision, context length - Custom model upload and registration - Model search by name/category Flutter SDK: - Model registry APIs: listModels, getModel, searchModels - Custom model upload with multipart upload - Training APIs: train(), fineTune(), trainStream() - TrainingOptions: framework, epochs, batch_size, learning_rate - TrainingProgress for real-time updates - ModelUploadOptions and ModelUploadResult Example code for: - Listing available models by category - Fine-tuning pre-trained models - Uploading custom Python/ONNX models - Streaming training progress This enables users to: 1. Use pre-registered models like 'llama-3-70b' 2. Upload their own custom models 3. Fine-tune models on custom datasets 4. Track training progress in real-time	2026-01-11 15:22:26 +05:30
Gulshan Yadav	4c36ddbdc2	feat(compute): add Phase 11 Synor Compute L2 heterogeneous compute layer - Add synor-compute crate for heterogeneous compute orchestration - Implement processor abstraction for CPU/GPU/TPU/NPU/LPU/FPGA/DSP - Add device registry with cross-vendor capability tracking - Implement task scheduler with work stealing and load balancing - Add energy-aware and latency-aware balancing strategies - Create spot market for compute resources with order matching - Add memory manager with tensor handles and cross-device transfers - Support processor capability profiles (H100, TPU v5p, Groq LPU, etc.) - Implement priority work queues with task decomposition Processor types supported: - CPU (x86-64 AVX512, ARM64 SVE, RISC-V Vector) - GPU (NVIDIA CUDA, AMD ROCm, Intel OneAPI, Apple Metal) - TPU (v2-v5p, Edge TPU) - NPU (Apple Neural Engine, Qualcomm Hexagon, Intel VPU) - LPU (Groq Language Processing Unit) - FPGA (Xilinx, Intel Altera) - DSP (TI, Analog Devices) - WebGPU and WASM runtimes	2026-01-11 13:53:57 +05:30

Author

SHA1

Message

Date

Gulshan Yadav

89fc542da4

feat(compute): add model registry and training APIs

Adds comprehensive model management and training capabilities:

synor-compute (Rust):
- ModelRegistry with pre-registered popular models
  - LLMs: Llama 3/3.1, Mistral, Mixtral, Qwen, DeepSeek, Phi, CodeLlama
  - Embedding: BGE, E5
  - Image: Stable Diffusion XL, FLUX.1
  - Speech: Whisper
  - Multi-modal: LLaVA
- ModelInfo with parameters, format, precision, context length
- Custom model upload and registration
- Model search by name/category

Flutter SDK:
- Model registry APIs: listModels, getModel, searchModels
- Custom model upload with multipart upload
- Training APIs: train(), fineTune(), trainStream()
- TrainingOptions: framework, epochs, batch_size, learning_rate
- TrainingProgress for real-time updates
- ModelUploadOptions and ModelUploadResult

Example code for:
- Listing available models by category
- Fine-tuning pre-trained models
- Uploading custom Python/ONNX models
- Streaming training progress

This enables users to:
1. Use pre-registered models like 'llama-3-70b'
2. Upload their own custom models
3. Fine-tune models on custom datasets
4. Track training progress in real-time

2026-01-11 15:22:26 +05:30

Gulshan Yadav

4c36ddbdc2

feat(compute): add Phase 11 Synor Compute L2 heterogeneous compute layer

- Add synor-compute crate for heterogeneous compute orchestration
- Implement processor abstraction for CPU/GPU/TPU/NPU/LPU/FPGA/DSP
- Add device registry with cross-vendor capability tracking
- Implement task scheduler with work stealing and load balancing
- Add energy-aware and latency-aware balancing strategies
- Create spot market for compute resources with order matching
- Add memory manager with tensor handles and cross-device transfers
- Support processor capability profiles (H100, TPU v5p, Groq LPU, etc.)
- Implement priority work queues with task decomposition

Processor types supported:
- CPU (x86-64 AVX512, ARM64 SVE, RISC-V Vector)
- GPU (NVIDIA CUDA, AMD ROCm, Intel OneAPI, Apple Metal)
- TPU (v2-v5p, Edge TPU)
- NPU (Apple Neural Engine, Qualcomm Hexagon, Intel VPU)
- LPU (Groq Language Processing Unit)
- FPGA (Xilinx, Intel Altera)
- DSP (TI, Analog Devices)
- WebGPU and WASM runtimes

2026-01-11 13:53:57 +05:30

2 commits