Commit graph

3 commits

Author SHA1 Message Date
Gulshan Yadav
dcd1cccc67 style: apply cargo fmt formatting 2026-02-02 05:58:22 +05:30
Gulshan Yadav
7e3bbe569c fix: implement incomplete features and apply linter fixes
- Fixed TransferDirection import error in ethereum.rs tests
- Implemented math.tanh function for Flutter tensor operations
- Added DocumentStore CRUD methods (find_by_id, update_by_id, delete_by_id)
- Implemented database gateway handlers (get/update/delete document)
- Applied cargo fix across all crates to resolve unused imports/variables
- Reduced warnings from 320+ to 68 (remaining are architectural)

Affected crates: synor-database, synor-bridge, synor-compute,
synor-privacy, synor-verifier, synor-hosting, synor-economics
2026-01-26 21:43:51 +05:30
Gulshan Yadav
4c36ddbdc2 feat(compute): add Phase 11 Synor Compute L2 heterogeneous compute layer
- Add synor-compute crate for heterogeneous compute orchestration
- Implement processor abstraction for CPU/GPU/TPU/NPU/LPU/FPGA/DSP
- Add device registry with cross-vendor capability tracking
- Implement task scheduler with work stealing and load balancing
- Add energy-aware and latency-aware balancing strategies
- Create spot market for compute resources with order matching
- Add memory manager with tensor handles and cross-device transfers
- Support processor capability profiles (H100, TPU v5p, Groq LPU, etc.)
- Implement priority work queues with task decomposition

Processor types supported:
- CPU (x86-64 AVX512, ARM64 SVE, RISC-V Vector)
- GPU (NVIDIA CUDA, AMD ROCm, Intel OneAPI, Apple Metal)
- TPU (v2-v5p, Edge TPU)
- NPU (Apple Neural Engine, Qualcomm Hexagon, Intel VPU)
- LPU (Groq Language Processing Unit)
- FPGA (Xilinx, Intel Altera)
- DSP (TI, Analog Devices)
- WebGPU and WASM runtimes
2026-01-11 13:53:57 +05:30